1. Field of the Invention
The present invention relates to a semiconductor circuit device and, specifically, to a semiconductor circuit device for decoding a plurality of signals to generate a signal selecting a selection object element. More specifically, the present invention relates to a construction for speeding up a decoding circuit for decoding a plurality of address signals.
2. Description of the Background Art
In a semiconductor device, a circuit is widely used which selects one of a plurality of object circuits or elements according to a selection signal. A typical example of such a selection circuit is an address decoding circuit, which generates a signal for selecting data in an addressed storage location according to an address signal in a semiconductor memory device.
In a SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), a non-volatile memory or other memory, memory cells are arranged in rows and columns. Generally, in accessing data, a row and a column of a memory cell are selected according to an address signal, to select a memory cell at the addressed location, and data is written to or read from the selected memory cell.
Unit address decoding circuits are arranged corresponding to rows and columns of memory cells, to select a memory cell. Here, structures of a memory block, a memory bank and others are not considered. The most simple memory cell array structure is considered, for simplicity of description. A pre-assigned set of address signals are applied to each of the unit address decoding circuit. The unit address decoding circuit corresponding to an addressed row or column is selected, and a selection signal for the corresponding row or column is activated.
The unit address decoding circuits in such an address decoding circuit have the same structure. Thus, circuits of the same structure are repeatedly arranged corresponding to memory cell rows or columns. A combination of address signals is different for different decoding circuit. A layout is simplified by repeatedly arranging circuits of the same structure. As the same patterns are repeatedly arranged, patterning of the circuits becomes accurate and easy, which results in the same circuit operation characteristics.
In a semiconductor memory device, a data access is needed to be made as fast as possible. To achieve such a high-speed access, it is required to decode an address signal and drive the addressed row or column to a selection state as quickly as possible. A word line shunt structure, in which a word line is lined by a metal interconnection line of an upper layer, is used, in some cases, to quickly drive the word line arranged corresponding to a memory cell row to a selection state. Examples of such a word line shunt structure are shown in a prior art reference 1 (Japanese Patent Laying-Open No. 8-321590) and a prior art reference 2 (Japanese Patent Laying-Open No. 7-307446). By electrically connecting a word line formed of polysilicon (polycrystalline silicon) or the like of a relatively high resistance with a metal interconnection line of a low resistance, the resistance of the word line is equivalently reduced, and a word line drive signal (or a word line selection signal) is transmitted from a proximal end to a distal end of the word line at high speed.
To select a memory cell at high speed, it is required to perform an address decoding operation as well at high speed. In regard to an address signal, as a unit decoding circuit is arranged corresponding to each memory cell row or column, a large number of decoding circuits are connected to an address signal line, which results in the large load on the address signal line. In addition, as the address signal line is arranged in common to the large number of decoding circuits, the interconnection becomes longer. Therefore, a line capacitance and a resistance of the address signal, or an RC time constant become greater, and thus the address signal cannot be switched at high speed, resulting in a longer access cycle time. Particularly, when the address signal statically changes as in a static random access memory (SRAM), this delay in the change of the address signal significantly affects an operation cycle time.
In addition, because of a signal propagation delay due to a capacitance and a resistance of the address signal line, arrival times of address signals at decoding circuits differ between a proximal end and a distal end of the address signal line, and accordingly, actual decoding operation start timings of unit decoding circuits differ. Therefore, definition timings of the decoding results of the address signals are different depending on positions of the unit decoding circuits, and as an operation start timing of a subsequent circuit such as a word line drive circuit is determined based on an output signal of the unit decoding circuit of the worst case, the high-speed access cannot be achieved.
Furthermore, when the operation timing of the subsequent circuit is made as fast as possible, a margin of the subsequent circuit to the worst case circuit is reduced, and an accurate operation cannot be ensured.
Such a decrease in operation speed due to increased load of the signal line typically appears in an address signal in a semiconductor memory device. In other decoding circuit which generates a signal of generating a selection signal or designating an operation mode according to a control signal as well, however, generally a large number of circuits of the same structure (repetitive circuits) are connected to a single signal line, and thus the load of the signal line becomes greater and the signal line cannot be driven at high speed.
The above-descirbed prior art reference 1 discloses a structure, in which both ends of each of word lines arranged on symmetrical positions of two memory arrays are connected by metal lining interconnection lines in a mask ROM (Read Only Memory). This reference 1, however, does not consider speeding up of a decoding circuit itself which drives the word line and the disadvantage of the address signal load at all. Although reduced resistance of a whole word line through lining (backing) by metal interconnection is described, the problem of distribution of the signal propagation delay on a single word line is not considered.
In the above-descirbed prior art reference 2, lining metal interconnection segments are discretely arranged for one word line such that the lining metal interconnection segments in adjacent word lines are arranged on different positions. With the discrete arrangement, it is intended to decrease a pitch of the lining metal interconnection in a column direction, and correspondingly, to decrease a pitch of the word lines. In this structure, however, regions lined and not lined by the metal interconnection exist in a single word line, and signal propagation delays distributes over one word line. Therefore, in the structure of the prior art reference 2, the portion of the high-resistance, lower-layer word line which is not lined exerts a significant effect, and thus the whole word line cannot be driven to a selected state at high speed.
In the prior art reference 2, there also is no discussion on implementing a faster decoding operation timing by changing an address signal at high speed in a circuit of decoding the address signal, and the problem of the address signal propagation delay is not considered at all.
An object of the present invention is to provide a semiconductor circuit device that can transfer a signal to be decoded to a distal end of a signal line at high speed.
Another object of the present invention is to provide a semiconductor circuit device that can sufficiently decrease a difference in signal arrival times at decoding circuits.
A semiconductor circuit device according to the present invention includes a plurality of first interconnection lines respectively arranged corresponding to a plurality of signals, a plurality of second interconnection lines respectively arranged corresponding to and in parallel with the first interconnection lines, each second interconnection line being electrically connected to a corresponding first interconnection line at a prescribed position and transmitting a corresponding signal to the corresponding first interconnection line, and a plurality of logic circuits formed in a lower layer region below the first interconnection lines, each logic circuit receiving a signal of a predetermined interconnection line of the plurality of first interconnection lines and logically processing the received signal to generate an output signal.
A first interconnection line is connected with a plurality of logic circuits and is accompanied with the large load and the large signal propagation delay. On the other hand, a second interconnection line is not connected to a logic circuit and can transmit the signal at high speed. By electrically connecting the first and second interconnection lines at a prescribed position, a signal can be transmitted to a distal end of the first interconnection line through the second interconnection line, and accordingly, an RC delay due to a resistance and a capacitance of the first interconnection line can equivalently decrease. Thus, a variation in signal propagation delay of the first interconnection lines among the logic circuits can be decreased, and the signal can quickly be changed to perform an actual decoding operation at a faster timing.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.